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Please find the JD Below:
Physical Design Engineer/ Sr. Physical Design Engineer
Experience : 3yrs to 8Years
Location: Bangalore
Skill: Physical Design
3+ year’s Experience in Physical Design engineering
Experience serving as Senior physical design engineer or SOC or block coordinator or top level integrator in TSMC 12m or 16nm process and beyond required
Experience running Synthesis-to-GDS ready flows, advanced timing flows and power-driven PD flows (e.g., multi-domain designs with a UPF/CPF flow) , Strong expertise on low power methodology in FinFET design, shared NWELL methodology is highly desirable
Experience in Cadence design flow is highly desirable/flat and hierarchical flow/STA timing signify/PV and PI signoff/ multi-bit flops/Retention flops
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