Senior Design Verification Engineer

  • Hyderabad
  • Teksystems

1. Good verification skills (Verilog, system Verilog).

2. Strong Knowledge of UVM methodology, with hands on experience of coding testbenches. with Good debug skills.

3. AMBA – (AXI, AHB, APB) – Good to have protocol knowledge

4. Exposure to Arm based SOC preferred but not a must

4. Well versed with digital design fundamentals

5. Scripting – perl, tcl, Make, shell scripting