Design Enablement Team (DET) Manager

Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.JR49776 Design Enablement Team (DET) Manager (Evergreen)Responsibilities include but not limited to the followingManage a team of Design Enablement Leads (DELs) who are responsible for development of Design Rules, Requirements, Test Structures and improve process margin for all DRAM generations from early development until manufacturing ceases, by coordinating with engineers from multiple groups and across several geographiesDefine milestones for projects within the layout schedule and work with the various teams to achieve the targets and time-linesPartner with Design, Product Engineering, Process integration, Business Units and Quality groups to optimize PPAC (Performance, Power, Area, Cost) for all Micron DRAM productsStrategically partner with multiple teams and fields to understand process issues related to the database layout, and prioritize development of solutions with Process Integration, Advanced Mask Design, Scribe & Frame, Layout & DesignDrive effort to build and evaluate test structures to provide data for next generation devices and to quantify process margin on current devicesSummarize sophisticated problems, derive and explain actions taken to address themDrive effective multi-functional communication on issue resolution, and support across node Design Rule alignmentMaintain and implement meaningful communication between Process Integration, Product Engineering, Design, and Advanced Mask teamsImprove timely documentation of the R&D activities with regard to design rule improvements for transfer to parts still in designDFM, pitch cell improvement, etc. for test structure. Validate and improve existing design rule by using test structure char and analysis.Minimum QualificationsBS/MS/PhD in Electrical Engineering, Microelectronics, Physics or related fieldSenior level (10+ years) experience in the semiconductor industry in the areas of Process Integration, Yield Enhancement, Product Engineering, Design, Test Structure Development, or Unit Process DevelopmentElectrical test structure layout and characterization experienceProcess integration or Design or Product Engineering experience a plusExperience managing a technical team a plusAble to manage complex programs across multiple geographies and different cross-functional groups.Solid grasp and exposure to design & layout with the ability to do minor layout, work with Pcells is desiredSuccess in resolving sophisticated issuesThink and communicate clearly in urgent and stressful situationsAdvantageous to have an understanding of DRAM process flow, as well as the function and purpose of major DRAM components, such as Sense Amp, Word-line driver, and Anti-FuseExposure and familiarity with CAD group interactions, data post-processing, and the process of transferring data from the database to the reticle