Principal Design Engineer(Memory IP Verification )

Responsibilities: · Contribute to IP verification execution, own verification schedule and deliverables. · Understand design specification, define verification TB architecture, create verification plan and environment. · Participate in technical discussions and represent verification team in all the discussions with internal and external customers. · Fully accountable for quality design verification as per the schedule. · Track the verification progress, identify potential risks, and mitigation plan. · Review all technical deliverables from team members and guide team members to meet quality and the schedule. · Mentor and provide technical guidance to team working in the projects. · Contribute to verification process and methodology improvements to boost efficiency and productivity. Requirements/Qualifications: · Bachelor's/Master's degree in Electronics/Electrical Engineering · 7+ years of Design verification experience with SV/UVM · IP verification experience memory IP (DDR/HBM) domain, In-depth understanding of design architecture features and used cases. · Sound verification knowledge of mixed-signal design at Verilog and AMS level. · Should have knowledge on all aspects of verification components & verification metrics · Hands-on experience on block, IP and system level verification. · Should have involved in IP verification from verification plan to final verification signoff for minimum of 2-3 IPs. · Should have flair for documentation, defining/improving methodology and achieving productivity improvement. · Good on project planning, resource estimate and breaking verification work into independent tasks. Identify potential risks, present/discuss risks, problems, mitigation plan with project stake holders. · Expert on coverage driven verification methodology, functional and code coverage closure. · Hand-on experience on GLS and SDF verification · Reasonable in communication and interpersonal skills, demonstrate teamwork and collaboration skills.