Analog Design Engineer

Role Summary: The Analog Circuit designer will be responsible for designing various components of high speed serial link like USB3, USB4, DP etc. The individual is responsible for design, verification and evaluation of those. The individual is accountable for designing according to specifications, quality and reliability needs. Participation in problem solving for Analog and system domain of the device. Author of the design-specific documentation for internal and external use. Job Responsibilities: Must have prior experience in design of few circuit blocks among CTLE, DFE, CDR, PLL, P2S, S2P, DCC, Phase-interpolator, TX Driver, LFPS/SQ, AUX etc Need to have solid understanding of device physics Need to have solid understanding of foundational analog circuits like LDO, BG, comparator, charge pump etc Need to have good exposure in high speed custom digital design like latch, FF, clk divider, counter etc Should have experience in defining layout constraint and reviewing layout In this role, the candidate should provide innovative technical solutions to address design challenges leading to significant improvement of PPA Need to work with the system, verification (AMS, DV) and RTL design team in defining A/D interfaces, adaptation flow and calibration schemes End to end ownership of assigned design blocks Guide junior designers Documentation of design and presenting them to reviewers Job Qualifications: Master’s/Bachelor’s Degree in Electrical/Electronic engineering from a reputed, university with an emphasis in VLSI/IC design. 10+ years of extensive experience in design and development of high speed SerDes PHY in few of these blocks: Tx, Rx, Clocking sub-systems in multi Gbps serial link USB3.x, USB4, DP or Thunderbolt, HDMI, PCIe, Ethernet etc Experience in USB2 circuit design will be a plus point Hands on experience with at least one of these blocks: CDR, Tx Driver, RX CTLE, DFE, VGA, PLL Proficient in using analog circuit design EDA tools such as Cadence ADE, MATLAB, EMX, Momentum etc. Knowledge of System Verilog and VerilogA modelling would be appreciated Good knowledge of analog building blocks design and their tradeoff for power, area and jitter optimization. Good understanding of impedance matching, s-parameter, equalization, ISI, noise/jitter modelling and their simulations are desirable. Strong skills in bandwidth enhancement techniques, noise suppression and linearity improvement techniques will be treated as plus point. Excellent verbal and written communication skills are desired. A creative and innovative mindset and ready to understand new concepts, result driven and a good team player attitude is needed. Having technical publications and/or patents is a plus.