STA Engineer

Job Title: STA Engineer

Skills Required

· 3-10 years of relevant experience in Synthesis/STA

· Good knowledge and understanding of overall design Flow RTL to GDS.

· Hands on Experience on Constraints Generation, Management for hierarchical designs.

· Thorough Knowledge of DFT Constraints.

· Hand on Synthesis & STA Experience on Lower node Technologies with Synopsys/Cadence Tools.

· Hands on Experience on Equivalent Checks with Synopsys / Cadence Tools.

· Good knowledge on Timing Budgets.

· Knowledge on scripting languages like Perl / TCL / Python

· Good understanding of the Chip Interface Constraint Generation & Timing Closure.

· Hands on experience on power analysis using PTPX

· Good understanding of VHDL / Verilog Constructs.

Responsibilities

· Responsible for Block/ Chip Tile Synthesis to achieve the best PPA.

· Constraint Generation & Maintenance for Block / SOC for complex hierarchical Designs for all the Modes.

· Interaction with Design, DFT, IP&PD teams for Timing Convergence & Resolving Constraint Conflicts .

· Able to work on low power Intent & verify low power intent with minimal supervision.

· Responsible for Logical equivalence checks & Low Power Checks.

· Early RTL analysis for Clocking, Power , DFT coverage & suggestions to Designer on the improvements.

· Support Verification team to enable GLS.

Experience – 5 to 15 Years

Location: Hyderabad/Bangalore