.. design Entry for Schematic capturing. Component placement Definition and Construction of Layer stack up Constraint settings for power (Clearance\Creepage), HDI .. and test the proto boards. Knowledge to use oscilloscope, power supplies to test electronic circuits. Additional soft skills: Strong communication and .. read more
You will be a member of the Advanced Node Methodology Pathfinding team which is responsible for rapid (Power, Performance, Area) PPA closure on high-performance designs, using Fusion Compiler/IC Compiler II. You would be working very closely with R&D and Foundry Partners, and should be able to isolate potential issues to help enhance the algorithms to greatly improve PPA and Runtime for the customer’s specific designs.
We are seeking someone with 5-12 years of exp, who can understanding Foundry enablement needs, and tie them to PPA closure by upgrading capabilities of the EDA engines.
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