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Job Summary: We are in search of a skilled Design Verification Engineer with at least 4 years of practical experience. As an essential member of our team, you will have a crucial role in ensuring the strength and accuracy of our state-of-the-art System On Chip designs.
Primary Duties:
Practical verification experience in SOC Design Verification/IP Verification/Sub System Verification/SV-UVM for intricate projects, guaranteeing the successful implementation of verification plans.
Create and execute thorough verification strategies, test plans, and test benches for high-speed SOCs, encompassing low-speed peripherals such as I2C/I3C, SPI, UART, GPIO, QSPI, and high-speed protocols like PCIe, UCIe, Ethernet, CXL, MIPI, DDR, and HBM.
Perform Gate-level simulations, and power-aware verification using Xprop and UPF.
Minimum Requirements:
4+ years of hands-on experience in SOC Design Verification/IP Verification/Sub System Verification/SV-UVM for complex projects.
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