RTL Lead

Hi Folks

Greetings from Tech Mahindra!!

Role: RTL Lead Engineer

Exp: 8+ years

Location: Bangalore/ Kochi/ Vizag/ Ahemdabad

About Job

• Architecture Development
• Experience in developing High Level Architecture for a Design Requirement from Specification level
• Extract Micro Architecture from High Level Architecture specification
• RTL Design - Coding & Integration
• Develop the logic design and Implement register transfer level (RTL) coding for an IP / SoC design
• Optimize logic to qualify the design to meet power / performance / area / timing goals and ensure Design Integrity
• Build unit level tests to verify the initial design –
• Ensure designs are delivered on time and with the highest quality by using proper checks
• Provide Hand-off to Subsystem / SoC Owners for IP Integration
• Integrate logic of IP blocks and subsystems into a full chip SoC or discrete component design
• Work with different IP providers to integrate and validate IPs at the Subsystem or SoC level
• Review verification plan and implementation to ensure design features are verified correctly
• Work closely with Verification team on Feature Extraction, Test Plan Review & sign-off closures
• Resolve and implement corrective measures for failing RTL tests to ensure correctness of features
• RTL Quality Checks
• Perform quality checks on various logic design aspects ranging from RTL to timing/power convergence.
• Hands on experience in running Synopsys Fusion Compiler for Synthesis and Area and performance estimation
• Perform RTL Lint check, Equivalence checking, CDC checking and support Static Timing Analysis, Static Power Checks,
• Work closely with different Product owners (Design team / Tool Team / Vendors etc., ) to resolve Design (or) Flow issues
• Triage all violations for a given Quality check - Accurately Identify & Root Cause issues in design and provide solutions
• Own the RTL QC task for a given IP / Subsystem / SoC – Ensure periodic checks & Clean up issues with new RTL Drops iteratively
• EDA Tool Exposure :
• VCS Compile, SG Lint, SG CDC, Synthesis DC / FC Compiler
• VC LP, Conformal LEC, SAGE Coverage, Calibre, Fishtail
• Integration Tools - Collage / DeFacto
• Scripting & Automation Exposure
• Knowledge / Working Experience on Perl, Tcl, Shell scripting is an added advantage
• Knowledge / Working Experience on debugging Tool Flows & Setup related issues is an added advantage

• Protocol Knowledge (IPs / Processors / IO Bus Protocols etc., )
• Ability to Understand complex SOC architecture concepts through work experience
• Protocol Knowledge – PCIe, CXL, USB, Ethernet, DDR, HBM MIPI, RISC etc.,

To Apply: share your resume at AA00782415@techmahindra.com